1. Field of the invention
The present invention relates to a manufacturing method for semiconductor devices and more particularly to a method for forming a Field Effect Transistor (FET) on an SOI layer.
Methods for forming semiconductor devices on SOI layers are essential for improving the isolation characteristics of devices and also for allowing plural layers of semiconductor devices to be stacked atop each other.
Recently, shallow device regions have been formed, in order to realize a high speed operation of the device itself.
Semiconductor devices are typically formed on a device substrate (SOI layer) using, for example, an SOI (Silicon On Insulator) substrate which is formed by stacking thin device substrates on a thick substrate through a very thin oxide film.
In the case where an FET is formed on an SOI layer as a semiconductor device, the characteristics of a semiconductor layer, the insulation film on which the semiconductor layer is formed, and the characteristics of the interface between the semiconductor layer and the insulation film all importantly influence the characteristics of the FET. Accordingly, in order to improve the characteristics of an FET formed on an SOI layer, it is strongly advisable to improve the characteristics of the semiconductor layer and insulation film themselves, as well as the characteristics of the interface between the semiconductor layer and the insulation film.
2. Description of the Related Art
A schematic sectional view of an FET formed on an SOI film by conventional methods is shown in FIG. 1.
In FIG. 1, numeral 2 designates an insulation layer formed on a substrate 1. A semiconductor layer 3, isolated like an island, is formed on the insulation layer 2 (i.e. an isolated SOI layer) on which the FET is formed. A gate insulation film 4 covers the semiconductor layer 3. A gate electrode 5 is provided on the gate insulation film 4, and a source/drain region 6 is formed in the semiconductor layer 3. An insulation film 7 is formed on the surface of the gate electrode 5. Numeral 9 designates a metal wiring.
The above-described FET is formed by the following process: A semiconductor layer 3, isolated like an island, is formed by patterning a semiconductor layer (SOI layer) on the insulation layer 2. A gate insulation film 4 is formed on its surface, and thereafter a gate electrode film is deposited over the entire surface thereof and a gate electrode 5 is formed by patterning such a gate electrode film. Next, a source/drain region 6 is formed by selectively implanting ions within the island of the semiconductor layer 3. Thereafter an insulation film 7 is formed on the surface of gate electrode 5. However, selective ion implantation as described above, may also be conducted after formation of the insulation film 7.
As possible methods for forming the SOI substrate, for example, SIMOX wafer bonding SOI, and laser anneal single crystallization can be considered. Among these, in the SIMOX method, oxygen ions are implanted before hand to a comparatively deep area from the surface of a single silicon wafer by activating implanted oxygen through heating of the substrate, and the upper silicon layer partitioned by such an oxide layer is used as the element region. However, it is very difficult to form a high quality device region using this method. In addition, it has been proposed that a silicon layer be formed by chemical vapor deposition (CVD) on the surface of a supporting substrate comprising a silicon wafer, and this silicon layer is then melted once by laser annealing and then recrystallized. A single crystal silicon layer thus formed is used as the device region. However, it is also difficult, in this case, to form a high quality device region. Therefore, wafer bonding SOI has recently attracted much attention as a promising method for manufacturing an SOI substrate on which a high quality device region may be formed. In this method, two sheets of silicon wafers are prepared, an oxide film is formed on at least one of them, another silicon wafer is put on the surface of the oxide film, and the wafers are bonded, for example, by electrostatic bonding followed by annealing. Thereafter, the surface of one of the silicon wafers is ground, and the layer being left as a thin layer is used as the device region.
However, even when a wafer bonding SOI method is employed to form a high quality SOI substrate as the device region, it is difficult to form a device region (i.e. the isolated semiconductor layer 3) thinner than about 1 .mu.m, because even when the silicon wafer is simply polished, the surface of the silicon substrate itself is currently not so flat that it can be formed with a thickness of 1 .mu.m. It is also difficult, from a technical viewpoint, to uniformly polish the silicon substrate surface up to a thickness of 1 .mu.m or less. It is also difficult, even by other SOI methods, to form the isolated semiconductor layer 3 conforming to design values having a thickness of 1 .mu.m or less, due to an excessively small process margin.
Accordingly, in a MOSFET which has been manufactured by the method described above, using such a wafer bonded SOI substrate, the drain current--voltage characteristics of the MOSFET, when the thickness of the semiconductor layer island 3 is formed to be about 1 .mu.m for easy manufacture, exhibits a so-called "kink" phenomenon in which the drain current suddenly increases as shown in FIG. 2 whenever a certain drain voltage is exceeded. Therefore, the circuit operations become unstable due to overshooting of the output voltage in AC operation of a source follower circuit.
It is known, however that such a kink phenomenon does not appear when the thickness of semiconductor layer island 3 is thin, i.e. about 0.1 .mu.m. However, formation of the thin SOI layer needed in order to produce such a thin semiconductor island 3 is always accompanied by technical difficulty.
Japanese Patent Laid-open No. 63-265469 discloses the following: Since a current flowing from the side or bottom surfaces of the Si layer island causes a subthreshold current in the FET, a structure for surrounding the area between the source and drain of the Si layer island with a doped polysilicon layer has been proposed in order to eliminate such a current. The polysilicon layer serves as a gate electrode through the SiO.sub.2 film. However, the structure disclosed by this method is formed by a process wherein the Si layer on which FET is formed is recrystallized in an area between the source and drain first by melting the Si layer and thereafter recrystallizing the Si layer with laser irradiation. Accordingly, an SiO.sub.2 film provided underneath the Si layer island is subjected to damage due to high temperatures in the recrystallization process. Therefore, in order to prevent such damage, the SiO.sub.2 layer is required to have a constant thickness, sufficiently resistive to such high temperatures. In other words, according to this method, the thickness of the gate oxide film cannot be controlled to a constant value or less. Accordingly, this method is not a practical method for forming an FET using SOI.